- Designed a secure inter-cloud pipeline using OIDC, AWS STS, AWS KMS, envelope encryption and TEE computing.
- Developed and debugged TEE-attestation validation flows across enclave startup, encrypted handoff, boot-state reporting, JWT/OIDC exchange, EC-key validation, trust-boundary checks and policy validation.
U.S. Citizen | Open to Relocation | ASIC Verification & RTL Design
Arnav Nevgi
Entry-Level Hardware Engineer | ASIC Verification | RTL Design | FPGA
Final-year B.Tech Electrical and Electronics student and U.S. citizen targeting entry-level hardware engineering roles in ASIC verification, RTL design, FPGA development and digital systems.
About
Hardware-focused, project-driven, and ready for entry-level engineering roles.
I am a final-year B.Tech Electrical and Electronics student focused on entry-level U.S. hardware engineering roles across ASIC verification, RTL design, FPGA development and digital systems. I bring 1+ year of internship experience and project work spanning SystemVerilog RTL, UVM verification, SVA, FPGA implementation, protocol-oriented design and waveform-based debug.
I am a U.S. citizen and open to relocating within the United States. I will be available for full-time employment after July 24, 2026. I also bring communication, collaboration and leadership experience from academic, internship, and project environments.
Professional Experience
Internship experience across secure systems, embedded hardware and board-level development.
- Contributed to secure bootloader development for a Caliptra-inspired HPC SoC platform, supporting trusted boot, firmware authentication, image validation, manifest parsing and anti-rollback checks.
- Validated secure boot and attestation scenarios using SHA hashing and ECDSA verification with mbedTLS.
- Designed and prototyped a multi-slot bio-incubator and BioCheq device, covering PCB design, BOM selection, STM32 and ESP32 I/O, sensors, power regulation, soldering, wiring and bring-up.
- Implemented embedded C firmware for sensor acquisition, GPIO expansion and slot-level control using shift registers.
- Implemented embedded C routines for GPIO sequencing, peripheral initialization, timing-driven control logic and serial communication.
- Supported board-level debugging and interface validation for embedded hardware workflows.
Projects
Selected digital hardware and verification work.
RISC-V SoC with AXI4 DMA and UVM Verification
ViewIntegrated a minimal RISC-V SoC with CPU-to-AXI adapter, 2-master and 2-slave AXI4 interconnect, burst DMA, AXI SRAM, DMA register slave, reset handling, and top-level integration. Built a UVM AXI verification environment with sequences, drivers, monitors, scoreboards, protocol SVA, functional coverage, constrained-random tests, and regression scripts.
SystemVerilog
UVM
SVA
AXI4
RISC-V
QuestaSim
2-Way Cache Memory Subsystem RTL with SECDED ECC and MBIST
ViewDesigned a 512B, 2-way set-associative cache with 16B lines, pseudo-LRU, write-back policy, dirty eviction, backing memory, SECDED ECC fault injection, and March C-minus MBIST. Verified hits, misses, dirty eviction, ECC fault-injection, and MBIST behavior using directed tests, 500 randomized transactions, protocol assertions, reference-model scoreboarding, waveform debug, regression logs, and 82%+ coverage.
SystemVerilog
SVA
Cache
ECC
MBIST
QuestaSim
Credit-Based NoC Router Arbiter with SVA Formal Verification
ViewDesigned a 4-port, 2-VC credit-based NoC arbiter with round-robin grants, backpressure control, and per-VC credit counters. Proved SVA properties using SymbiYosys, Yosys, and SMTBMC for grant validity, zero-credit blocking, credit bounds, pointer logic, bounded no-starvation checks, cover properties, reset recovery, and counterexample debug.
SystemVerilog
SVA
Formal Verification
SymbiYosys
Yosys
SMTBMC
FPGA UART IP Core with FIFOs and Timing Closure
ViewDesigned UART IP with TX/RX datapaths, 8N1 framing, 16x oversampling, configurable baud, FIFOs, loopback, and register interface. Verified functionality using SVA, scoreboards, directed and randomized tests, FIFO stress, frame-error injection, and overrun injection. Implemented RTL on Xilinx Artix-7 and Intel Cyclone V, meeting 100 MHz timing with positive setup slack.
SystemVerilog
FPGA
UART
Vivado
Quartus
SVA
Skills
Tools and concepts aligned with hardware engineering workflows.
Languages
SystemVerilog, Verilog, C, C++, Python, Tcl
Verification
UVM, SVA, functional coverage, scoreboards, constrained-random testing, waveform debug, regression testing
Protocols and Digital Design
AXI4, AXI4-Lite, UART, SPI, I2C, RISC-V ISA, memory-mapped interfaces, cache design, ECC, MBIST, NoC arbitration
Tools
QuestaSim, ModelSim, Vivado, Intel Quartus, GTKWave, SymbiYosys, Yosys, SMTBMC, Git, MATLAB, LTspice
Resume and Links
Role-focused resumes and profile links.
I maintain separate resume versions for ASIC verification/RTL-focused roles and FPGA/digital hardware-focused roles.
Contact
Open to entry-level U.S. hardware engineering roles.
I am open to entry-level U.S. hardware engineering roles in ASIC verification, RTL design, FPGA, and digital hardware.
f20220022@pilani.bits-pilani.ac.in